The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, in the mid-end-of-line (MEOL) processes, it is typical that gate via holes are etched in some areas that have dense vias and in some areas that have isolated vias. It is difficult to control via etching depth in both the dense and isolated via areas when the vias are partially etched. As a result, the via depth varies from one area to another. The via depth variation may cause issues in subsequent fabrication. For example, it may cause a leakage concern when gate contacts and source/drain (S/D) contacts are formed in a later step.